分享豪威精选笔试题

下面分享的是豪威笔试题目精选：
1 logic design
1.supposedly there is acombinational circuit between two registersdriven by a  clock.what will you do if the delay of the combinationalcircuit is greater than  the clock signal?
a.to reduce clock frequency b.to increase clock frequency
c.to make it pipelining d to make it multi_cycle
2.there is a fifo design which the clock of data input is running  at100mhz,while the clock of data output is running at 80mhz.the inputdata is a  fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200  clocks carry in no data.how big the fifoshould be in order to avoid data  over/under_run?please select theminimum depth below to meet the requirement.
A.160 b.200 c.800 d .1000
3.which of the follow circuits can generate gitch free gated_clk?
a.always@(posedge clk) gated <=en;assign gated_clk=gated&~clk;
b.always@(negedge clk) gated <=en;assign gated_clk=gated&~clk;
c.always@(posedge clk) gated <=en;assign gated_clk=gated|~clk;
d.always@(negedge clk) gated <=en;assign gated_clk=gated|~clk;
4.you’re working on a specification of a system with some  digitalparameters.each parameter has min,typ and max columns.which columnwould  you put setup and hold time?
a.setup time in max,hold time in min
b.setup time in min,hold time in max
c.both in max
d.both in min
5.there are 3 ants at 3corners of a triangle. They randomly startmoving  towards another corner.what is the probability that won’tcollide?
a.0
b.1/8
c/1/4
d.1/3
6.if you look at a clock and the time is 3:15.what is angle between the hour  and the minute hand?
a.0
b.360/48
3.360/12
d.360/4
7.how many times per day a clock’s hands overlap?
a.11
b.22
c.24
d.26
8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q=1ns.what is the max clock  frequency the circuit can handle?
A.200mhz
b.250mhz
c.500mhz
d.1ghz
2.physical design
1.before tape-out,which routine check should be performed for your layout  database in 0.18 um process?
a.drc
b.lvs
c.drc&antenna
e.simulation
2.how to fix antenna effect?
a.make the wire wider and shorter
b.change lower metal to upper metal
c.connect with diode of metal and diffusion
d.change upper metal to lower metal
e.b&c
3.please expain lvs
a.logic versus schematic
b.layout versus schematic
c.layout via synthesis
d.logic via synthesis
4.how to control clock skew?
a.get balanced clock tree
b.decrease the fanout
c.add clock buffer evenly
d.decrease clock latency
5.how to avoid hold_time violation?
a.lower the clock speed
b.the clock arrive later
c.the clock arrive earlier
d.the data arrive later
e.the data arrive earlier
6.what kinds of factors reflect good floor plan?
a.easy routing
b.easy timing met
c.enough power supply
d.a&b
e.a&b&c
7.what cause cell delay?
a.input-pin transition time
b.output-pin capacitance.
c.output-pin resistance
d.a&b
e.b&c
8.why need i/o pads for each chip?
a.esd protection
b.voltage level shift
c.latch-up prevention
d.a&c
e.a&b&c
9.which one is worse-case in 0.18um process?
1.1.8v,25c
2.1.98v,125c
3.1.62v,-40c
4.1.62v,125c
5.1.98v,-40c
10.if power plan is not good,what’ll happen to the chip?
a.hot-spot
b.voltage drop
c.timing not met
d.routing is tough
e.all of above
3.architecture design
1..compare two images,the first image has a person in front of ablackboard in  a classroom and the second image has a person in front ofa lush garden.the two  images are compressed using the jpeg algorithm.
a.the first image will have larger file size.
b.the second image will have a larger file size.
2.how would you round a 10b number,x,at the 3rd(上角)bit?
a.(x>>2)<<2.
b.(x>>3)<<3.
c.((x+4)>>2)<<2
d.((x+4)>>2)<<3
e.((x+8)>>2)<<3
f.((x+8)>>3)<<3
3.what happens if the number in 2 is negative?
A ignore
b.make it absolute ,do the operation in 2,and add sign back
c.none of the above
4.how would you multiply a 4 in hardware?
a.use 4 adders each is offset from the provious adder by 1bit.
b.use a booth multip;ier with 4b coefficient.
c.use wires.
d.use a barrel shifter.
5.how would you design a barrel shifter?
a.use multiple stages of 2乘2 multiplexers
b.use a crossbar switch that can switch any inputs to any outputs
c.use a clos network
d.have muxes to switch between all combinations of hardwired shifts.
6.what is a fifo?what is a filo?which one is a queue? Which one is a  stack?
a.fifo is a queue and filo is a stack.
b.fifo is the name of a dog. Filo is the name of a cat.
c.fifo is a stack and filo is a queue.